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AR# 12837

4.1i CPLDFit - An XCR3032XL-5 speed table flaw causes timing simulation hold violations

Description

Keywords: 4.1i, WebPACK, XPLA3, CoolRunner, XCR3032XL, -5, timing, simulation

Urgency: Hot

General Description:
According to the XCR3032XL-5 data sheet numbers, a register transition propagates through the feedback path so quickly that it violates the hold time on the same and other flip-flops.

As a result, timing simulations in the software sometimes fail with hold-time violations for a valid design pattern with valid waveforms.

Solution

The hold time specification will be decreased from 4ns to 3.5ns.

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 3.
AR# 12837
Date Created 10/10/2001
Last Updated 07/05/2006
Status Archive
Type General Article