We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 12838

4.1i NGD2VHDL - When NGD2VHDL is used with the -r switch, incorrect logic is produced (VHDL)


Keywords: NGD2VHDL, -r, retain, hierarchy, VHDL, simulation, timing

Urgency: Standard

General Description:
In a design, if one output PORT is driving another output PORT, the timing simulation netlist in VHDL will be incorrect.


This problem is fixed in the latest 4.1i Service Pack, available at:
The first service pack containing the fix is 4.1i Service Pack 2.
AR# 12838
Date 08/15/2003
Status Archive
Type ??????