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AR# 12838

4.1i NGD2VHDL - When NGD2VHDL is used with the -r switch, incorrect logic is produced (VHDL)

Description

Keywords: NGD2VHDL, -r, retain, hierarchy, VHDL, simulation, timing

Urgency: Standard

General Description:
In a design, if one output PORT is driving another output PORT, the timing simulation netlist in VHDL will be incorrect.

Solution

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 2.
AR# 12838
Date 08/15/2003
Status Archive
Type ??????