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AR# 12852

12.1 Constraints - How do I constrain the paths to or from block RAM when I use two different clocks?


How do I constrain the paths to or from block RAM when clocking at two different frequencies?


The software correctly traces the period specification through a block RAM instance, so only the period constraints for each respective clock must be specified as follows:

NET "clkd2" TNM_NET = "ts_clkd2";

NET "clk" TNM_NET = "ts_clk";

TIMESPEC TS01 = PERIOD ts_clkd2 10;

TIMESPEC TS02 = PERIOD ts_clk 5;

For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf

AR# 12852
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article