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AR# 12859

4.1i Virtex-II PAR - Clock routing fails to meet a MAXSKEW constraint

Description

Keywords: skew, maxskew, timing, clock, routing

Urgency: Hot

General Description:
Cases have been seen involving two separate but related clock-routing problems:

1. The router was not meeting MAXSKEW constraints in cases where the 3.1i tools worked successfully.

2. The router was not consistently following the USELOWSKEWLINES constraint by using a LOWSKEW template. (Please see (Xilinx Answer 12954) for more information.)

Solution

Both problems will be fixed in the 4.2i software release, which is currently scheduled for late February, 2002.

Meanwhile, a patch is available for use with 4.1i SP3:

PC:
http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/4.1i_par_pc_12859.zip

Unzip in the Xilinx install directory while maintaining directory structure.

Solaris:
http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/4.1i_par_sol_12859.tar.gz

cd $XILINX
gzip -d 4.1i_par_sol_12859.tar.gz
tar xvf 4.1i_par_sol_12859.tar
AR# 12859
Date Created 08/29/2007
Last Updated 10/20/2008
Status Archive
Type General Article