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AR# 12866

Virtex/-E/-II, Spartan-II/-IIE - What data rates can be achieved with the various I/O standards supported by these devices?


General Description:

The SelectI/O feature of Virtex/-E/-II and Spartan-II/-IIE FPGAs provides support for a number of different I/O standards. What speeds can be achieved with these standards? Are some faster than others? How do I know which one to choose for my application?


Xilinx is unable to specify maximum data rates supported by the various I/O standards, as the performance of any PCB data or clock path is dictated by a number of variables that can only be accounted for through accurate IBIS simulation and power network analysis. Briefly, these variables are:

- Output buffer characteristics. For more information, please see (Xilinx Answer 11863).

- PCB trace parameters such as characteristic impedance, length, and termination.

- Timing requirements of the design. For example, double data rate (DDR) requires a perfect 50/50 duty cycle, and duty-cycle distortion is common at high speeds.

- Jitter, including clock-source jitter, jitter added by Digital Clock Managers (DCMs) and Delay-Locked Loops (DLLs), jitter caused by SSOs, jitter caused by crosstalk-induced delay variations on the PCB traces, and jitter added by external components such as PLLs.

- The amount of noise present in the system, which is related to the following:

Power consumption (always design-dependent in programmable devices)

Power supply bypassing

Outside EMI sources

Crosstalk on the PCB traces

Simultaneous switching outputs (SSOs)

Xilinx provides IBIS models for simulating data and clock paths on the PCB. However, there are some limitations on the information that IBIS models can provide. For more information, please see (Xilinx Answer 3359) or visit the IBIS Home Page at http://www.eigroup.org/ibis/ibis.htm

Xilinx IBIS models can be downloaded here: http://support.xilinx.com/support/sw_ibis.htm

AR# 12866
Date Created 08/29/2007
Last Updated 02/05/2013
Status Active
Type General Article