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AR# 12885

ASYNC_FIFO_V3_0 - "Warning: Port size mis-match on output port Q (port number 16)..."

Description

When I compile a project, I receive the following warnings:  

 

"Warning: port size mis-match on output port Q (port number 16) (/tools/xilinx/4.1i_sp1/SunOS/verilog/src/XilinxCoreLib/ASYNC_FIFO_V3_0.v line 1255)" 

 

"Warning: port size mis-match on input port L (port number 4) (/tools/xilinx/4.1i_sp1/SunOS/verilog/src/XilinxCoreLib/ASYNC_FIFO_V3_0.v line 1264)" 

 

"Warning: port size mis-match on input port IV (port number 5) (/tools/xilinx/4.1i_sp1/SunOS/verilog/src/XilinxCoreLib/ASYNC_FIFO_V3_0.v line 1265)"

Solution

This problem has been fixed in Asynchronous FIFO v4_0, which is available with 4.1i IP update #1 (E_IP1). 

 

IP updates are available at: 

http://www.xilinx.com/ipcenter/coregen/updates.htm

AR# 12885
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article