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AR# 12946

7.0 SYNPLIFY - Problem involving instantiated BUFGCEs

Description


General Description:

Synplify 7.0 does not recognize an instantiated BUFGCE as a clock buffer; therefore, Synplify 7.0 will infer an IBUF instead of an IBUFG for the PAD.

Solution


VHDL Example



BUFGCE instantiation using Synplify:




library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;



entity bufgce_instantiate is

port ( clk_pad : in std_logic;

ce : in std_logic;

a : in std_logic_vector(15 downto 0);

b : in std_logic_vector(15 downto 0);

p : out std_logic_vector(31 downto 0) );

attribute xc_padtype: string;

attribute xc_padtype of clk_pad: signal is "IBUFG";



-- this attribute forces external clock pad signal to be of type IBUFG instead

-- of IBUF inferred by default by Synplify



end entity bufgce_instantiate;



architecture structural of bufgce_instanciate is



signal clk : std_logic;



component BUFGCE

port ( O : out std_logic;

CE : in std_logic;

I : in std_logic );

end component;



begin



-- BUFGCE instanciation

U1: BUFGCE

port map ( O => clk,

CE => ce,

I => clk_pad);



-- other code

process (clk)

begin

if rising_edge(clk) then

p <= a * b;

end if;

end process;



end architecture structural;



Verilog Example



BUFGCE instantiation using Synplify:




module bufgce_instantiate (clk_pad, ce, a, b, p);

input clk_pad /* synthesis xc_padtype = "IBUFG" */;

input ce;

input a;

input b;

output p;



wire clk;



BUFGCE U1 (.O(clk), .CE(ce), .I(clk_pad));



always @(posedge clk) p <= a * b;



endmodule
AR# 12946
Date Created 08/29/2007
Last Updated 01/20/2011
Status Archive
Type General Article