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AR# 12953

7.0 Synplify - Synplify is not preserving instantiated FDRE, FDR, FDSE, or FDS primitives

Description

Keywords: Virtex, Virtex-II, System Generator, FDR, FDS, preserve, primitive

Urgency: Hot

General Description:
My Virtex design contains synchronous set/reset flip-flops (FDR, FDRE, FDS, FDSE) primitives that are instantiated. However, after the mapping phase, Synplify replaces my instantiated primitives with FDs.

This problem is due to a bug in Synplify and Synplify Pro 7.0 that affects the instantiation of FDR, FDRE, FDSE or FDS primitives. This bug occurs when the control signals (the clock enable and the set/reset lines) for these flip-flops are connected to constants.

This problem was fixed in version 7.0.1. The latest version is available for download on the Synplicity web site at:
http://www.synplicity.com

To work around this problem, connect the ports to the signals/wires, then place a "syn_keep" attribute on the signals/wires:

Solution

1

VHDL example:

fdse_reg : FDSE
port map(c => clk,
d => in_sig,
q => out_sig,
ce => '1',
s => '0');

Setting the enable to "1" and the set to "0" allows this to behave like an ordinary FD component. Synplify sees this and changes it to an FD. This changes the power-up value of the register from "1" to "0". Because the FDSE is instantiated, Synplify should not change it.

A way to work around the issue, that does not require the patch, is to instantiate the component as:

signal zero : std_logic;
signal one : std_logic;

attribute syn_keep : Boolean;
attribute syn_keep of zero : signal is true;
attribute syn_keep of one : signal is true;

fdse_reg : fdse
port map(c => clk,
d => in_sig,
q => out_sig,
ce => one,
s => zero);

This issue is fixed in Synplify 7.0.1

2

Verilog example:

FDSE u1 (.D(d), .C(clk), .Q(q), .CE(1'b1), .S(1'b0));

Setting the enable to "1" and the set to "0" allows this to behave like an ordinary FD component. Synplify sees this and changes it to an FD. This changes the power-up value of the register from "1" to "0". Because the FDSE is instantiated, Synplify should not change it.

A way to work around this issue, that does not require the patch, is to instantiate the component as:

wire zero /* synthesis syn_keep=1 */;
wire one /* synthesis syn_keep=1 */;

FDSE u1 (.D(d), .C(clk), .Q(q), .CE(one), .S(zero));
AR# 12953
Date Created 08/29/2007
Last Updated 10/24/2005
Status Archive
Type ??????