When I compile a VHDL design that contains instantiated primitives, the following warning occurs:
"WARNING: <design>.vhd(#): No default binding for component: "<primitive>". (No entity named "<primitive>" was found.)"
When I load the design, the following warning occurs:
"** Warning: Component <name> is not bound."
When you instantiate primitives in a VHDL file, you must also add the following library statement to the file:
This error can also occur if the ISE Simulation libraries are not compiled or mapped correctly.
This error can also occur if the instantiation does not match the component declaration of the primitive. In this case, the error message will include information on which pins are missing.