We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1305

XC5200: BUFG - different skew between clock pin and non clock pin.


The BUFG of the XC5200 family of devices drives clock signal

to the flip-flops. A low skew is guaranteed, typically less

than 1ns.

The BUFG of the XC5200 family is also capable of driving non

clock signals such as CE or LUT (Look-up Table) inputs . The

skew between CLBs that are in the same column is still low.

However the skew between the CLBs placed in different columns

can increase if the fanout and/or the type of loading on the

vertical longline related to this global signal is differs

from one column to another.

For instance :

BUFG drives a signal 'global'. The signal 'global' is connect-

ed to CE of CLB_R1C1, CLB_R2C1, CLB_R3C1, and CLB_R1C2, and

also to LC0.F2 of CLB_R4C1, CLB_R5C1, and CLB_R6C1.

The skew on 'global' between CLBs in column 1 and CLBs in

column 2 could be greater than 1ns.


Having the same fanout/load on each vertical longline, can

reduce clock skew.
AR# 1305
Date Created 08/31/2007
Last Updated 08/26/2011
Status Archive
Type General Article