We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13087

4.1i Project Navigator - "ERROR: NgdBuild:25 - cannot both read and write file 'design.ngd'!"


General Description:

When I use the ABEL XST Verilog flow with a top-level schematic, NGDBuild fails and reports the following error:

"ERROR: NgdBuild:25 - cannot both read and write file "design.ngd"!"


When the ABEL XST Verilog flow is used, the "ngdbuild.rsp" file is missing a line that points to the input design; therefore, NGDBuild perceives that the .ngd file is both the input and output file.

To work around this problem, switch to the ABEL XST VHDL flow, which writes out an accurate .rsp file.

This issue was resolved in the 4.2i version of the ISE software.
AR# 13087
Date Created 08/29/2007
Last Updated 05/14/2012
Status Archive
Type General Article