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AR# 13121

Virtex-II, IFDDRRSE - How do I create an input Dual Data Rate (DDR) flip-flop and pack it into an IOB? (VHDL/Verilog)

Description

Keywords: Virtex-II, DDR, double data rate, input, IOB

Urgency: Standard

General Description:
How do I create a DDR register that can be put into the IOB on the input side? (The DDRCPE will not work as an input flip-flop.)

Solution

1

The following VHDL example illustrates the creation of an IFDDRCPE primitive.

VHDL

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;


--Define the entity.
--C0 and C1 are the input clocks.
ENTITY IFDDRSE IS
PORT
(
PRE,DIN,CE,C0,C1,CLR : IN STD_LOGIC;
Q0,Q1: OUT STD_LOGIC
);

END IFDDRSE;

ARCHITECTURE xil_comps OF IFDDRSE IS

SIGNAL D: STD_LOGIC;

--Define the FF component.
COMPONENT FDCPE
PORT (
PRE,D,CE,C,CLR : IN STD_LOGIC;
Q: OUT STD_LOGIC
);
END COMPONENT;


--Define the IBUF.
COMPONENT IBUF
PORT (
I : IN STD_LOGIC;
O : OUT STD_LOGIC
);
END COMPONENT;

attribute IOB : string ;
attribute IOB of U0 : label is "TRUE";
attribute IOB of U1 : label is "TRUE";

BEGIN
--Define the first FF.
U0: FDCPE
PORT MAP (
PRE=> PRE,
D=>D,
CE=> CE,
C=> C0,
CLR=> CLR,
Q => Q0
);


--Define the second FF.
U1: FDCPE
PORT MAP (
PRE=> PRE,
D=>D,
CE=> CE,
C=> C1,
CLR=> CLR,
Q => Q1
);

buff0: IBUF
PORT MAP (
I => DIN,
O => D
);

end xil_comps;

In version 5.1i, the IFDDR components are now primitives. The Libraries Guide contains component declaration and instantiation examples. To access the Libraries Guide, please refer to the online software manuals at:
http://support.xilinx.com/support/sw_manuals/xilinx5/

2

The following Verilog example illustrates the creation of an IFDDRCPE primitive.

Verilog

// Module Declaration

module IFDDRSE ( PRE,DIN,CE,C0,C1,CLR,Q0,Q1);

input PRE;
input DIN;
input CE;
input C0;
input C1;
input CLR;
output Q0;
output Q1;


reg D;

// clock buffer
IBUF buff0( D,DIN );

//IOB register

FDCPE U0
(
.PRE(PRE),
.D(D),
.CE(CE),
.C(C0),
.CLR(CLR),
.Q(Q0));


//IOB register

FDCPE U1
(
.PRE(PRE),
.D(D),
.CE(CE),
.C(C1),
.CLR(CLR),
.Q(Q1));


//exemplar attribute U0 IOB TRUE
//exemplar attribute U1 IOB TRUE
endmodule

In version 5.1i, the IFDDR components are now primitives. The Libraries Guide contains component declaration and instantiation examples. To access the Libraries Guide, please refer to the online software manuals at:
http://support.xilinx.com/support/sw_manuals/xilinx5/
AR# 13121
Date Created 08/29/2007
Last Updated 10/01/2008
Status Archive
Type General Article