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AR# 13164

3.x FPGA Express - "Error: Signal or port name expected as actual in association element. (VSS-806)"

Description

Keywords: FPGA Express, Orcad, Port, VHDL, 4.1i

Urgency: Standard

General Description:
I have assigned a port map as follows:

U0 : fmap PORT MAP(
I1 => A(8),
I2 => B(8),
I3 => ADD,
I4 => 'Z',
O => I8);

FPGA Express reports the following error message:

"Error: Signal or port name expected as actual in association element. (VSS-806)"

(This can be a major issue when using Cadence Orcad v14 to produce the VHDL file, as all open ports are assigned in this manner.)

Solution

This error is generated when a port map in a component instantiation statement associates an actual that is not a signal or a port name with a formal (that is a port name).

To work around this problem, create a dummy signal, assign this to Z, then map the non-connected ports to this signal.

For example:

signal high_Z : std_logic;

then assign this to Z

high_Z <= 'Z';

U0 : fmap PORT MAP(
I1 => A(8),
I2 => B(8),
I3 => ADD,
I4 => high_Z,
O => I8);
AR# 13164
Date Created 11/13/2001
Last Updated 08/11/2003
Status Archive
Type General Article