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AR# 13216

4.2i ISE Project Navigator - VHDL components are not picked up correctly

Description

Keywords: VHDL, order, components, XST, hierarchy

Urgency: Standard

General Description:
When I use a standard top-level VHDL code with XST, the top level does not pick up the lower level components if the instantiations of the components occur after a process.

Solution

1

This problem has been fixed in the ISE 5.1i software.

You may also work around the problem by changing the order of the VHDL code so the processes are located at the end.

2

The problem occurs because Project Navigator cannot correctly interpret the keyword component if this is used in the actual instantiation in the main body.

For example:

U1: component a
port map ( .....
);

This should be:

U1 : a
port map (....
);
AR# 13216
Date Created 11/19/2001
Last Updated 08/11/2003
Status Archive
Type General Article