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AR# 13223

4.1i SP3 - 4.1.03i Service Pack 3 update

Description

Keywords: Service, Pack, 4.1i, update, 4.1.03i, 3, SP3

This answer contains a list of changes included in the M4.1i Service Pack 3 update.

Solution

The Service Pack Update Page is located at:
http://support.xilinx.com/support/techsup/sw_updates/
The following issues are addressed by the 4.1i Service Pack 3 Update:

{SP} Denotes which Service Pack contains the fix

ABEL
{SP2 } (Xilinx Answer 12776): 4.1i CPLD - ABEL XST-Verilog flow fails for simulation with mixed-case top-module name.

BITGEN
{SP3 } (Xilinx Answer 13264): 4.1i BitGen - The warning "INFO:DesignRules:548..." should be issued only when DSS_MODE is not "NONE", but it appears even when DSS is not used.
{SP3} ( Xilinx Answer 12719): 4.1i BitGen - "ERROR: DesignRules:557 - Blockcheck: Invalid connection used between BUFGMUX and DCM...."
{SP3} ( Xilinx Answer 13261): 4.1i Virtex-II BitGen - "SRVAL_B" and "INIT_B" on BRAMs are programmed incorrectly.
{SP3} ( Xilinx Answer 13012): 4.1i Virtex-II BitGen - I need to be able to turn off the DCI clock after configuration (SSTL2, SSTL3 AM issue patch).
{SP3} ( Xilinx Answer 12688): 4.1i Virtex-E BitGen - Why does my DONE pin not go high when I use "startup_wait" for DLL locking?
{SP3 } ( Xilinx Answer 12579): 4.1i BitGen - "WARNING: BitGen:198 - CLKIN period 0ps is less than minimum of 2000ps."

{SP2 } (Xilinx Answer 12879): 4.1i Virtex-II BitGen - Bit streams for 2v4000 do not include BlockRAM initialization data.
{SP2 } (Xilinx Answer 12326): 4.1i Virtex-II BitGen - A patch is available to correct Virtex-II bit stream generation.
{SP2 } (Xilinx Answer 12887): 4.1i Virtex-II BitGen - Virtex-II IOB changes for HSTL1, HSTL2 HTSL1_DCI and HSTL2_DCI.

{SP1} (Xilinx Answer 12521): 4.1i Virtex-II BitGen - "Bitgen:218" warning message when XIL_BITGEN_VIRTEX2ES is set.

CHIP VIEWER
none

CONSTRAINTS EDITOR
{SP2 } (Xilinx Answer 12550): 4.1i Constraints Editor - LVDS CLK input is not shown as a clock.

{SP1} (Xilinx Answer 12550): 4.1i Constraints Editor - LVDS CLK input is not shown as a clock.

CPLD
{SP3 } (Xilinx Answer 12837): 4.1i CPLDFit - An XCR3032XL-5 speed table flaw causes timing simulation hold violations.
{SP3 } (Xilinx Answer 13267): 4.1CPLD CoolRunner-II - Pin-outs for all devices have changed.
{SP3 } (Xilinx Answer 12850): 4.1 WebPACK/ISE/WebFITTER - A Dr.Watson error occurs on "cpldfit.exe".
{SP3 } (Xilinx Answer 12913): 4.1i CPLD XPLA3 - "ERROR: top_level_timesim.sdf(1101): Instance 'x' does not have a generic named thold_i_clk_negedge_posedge'."

{SP2 } (Xilinx Answer 12043): 4.1i XPLA3 CPLDFit - The Port Enable pin is incorrectly declared as a "No Connect" in the report file.
{SP2 } (Xilinx Answer 12352): 4.1i XC9500XV CPLDFit - Core dump occurs during implementation of an XC9500XV design on an HP Workstation.
{SP2 } (Xilinx Answer 12775): 4.1i CPLD CPLDFit - A signal with both pin feedback and node feedback is not displayed correctly in the fitter report.

{SP1} (Xilinx Answer 12439): 4.1i CPLD XPLA3 CPLDFit - The Tf timing parameter has changed from 1.2 to 0.5ns for the XCR3032XL.
{SP1} (Xilinx Answer 12520): 4.1i CPLD XPLA3 - Timing constraints are not being obeyed.

ECS
none

FLOORPLANNER
{SP2 } (Xilinx Answer 12881): 4.1i Floorplanner - Floorplanner hangs when opening a file on AMD Athalon Processor PCs.

FOUNDATION
{SP3 } (Xilinx Answer 12487): 4.1i Foundation Series Install - Selecting "Help -> Online Documentation" generates the error "...index.htm does not exist".

FPGA EDITOR
{SP2 } (Xilinx Answer 12148): 4.1i FPGA Editor - The name filter tries to capitalize a search for "bufg*".
{SP2 } (Xilinx Answer 12880): 4.1i FPGA Editor - While routing, the default cleanup cost is set to 1.

FPGA Express
{SP2 } (Xilinx Answer 12101): 4.1i FPGA Express 3.6 LogiCORE PCI-X - Internal Error: Invalid value 'PCIX' for attribute 'pmap_iostd' on '/PCIX_TOP/...'.
{SP2 } (Xilinx Answer 12473): 3.6 FPGA Express - "Internal Error: Invalid value 'SLOW' for attribute 'pmap_slew' on 'component_name'."
{SP2 } (Xilinx Answer 12483): 3.6 FPGA Express - Bad logic generated from shift operator ">>" on a parameter in Verilog.
{SP2 } (Xilinx Answer 12100): 4.1i FPGA Express 3.6 LogiCORE PCI - "Internal Error: Invalid value 'SLOW' for attribute 'pmap_slew' on /pcim_top/AD..."

IMPACT
{SP3 } (Xilinx Answer 13263): 4.1i iMPACT - Encrypted bit streams produce strange errors regarding "StartupClk" and whether or not the bit stream is encrypted.
{SP3 } (Xilinx Answer 13265): 4.1i iMPACT - 9500xl/9500xv - SVF Programming fails.
{SP3 } (Xilinx Answer 12709): 4.1i iMPACT - 9572): "Error: The IDCODE read from the device does not match the BSDL file."
{SP3 } (Xilinx Answer 13260): 4.1i iMPACT - In batch mode, iMPACT crashes when assigning an .mcs file to an XC18V00 PROM.
{SP3 } (Xilinx Answer 13262): 4.1i iMPACT - "ERROR:Portability:3 - This Xilinx application has run out of memory..." occurs when I assign an XCR3512SL JEDEC file.
{SP3 } (Xilinx Answer 13266): 4.1i iMPACT-18V00 - "ERROR: IMPACT:223--'4': Calculated checksum differs from the expected checksum".
{SP3 } (Xilinx Answer 13268): 4.1i iMPACT CoolRunner XPLA3 - There is no programming support for the XCR3384XL-TQ144.

{SP2 } (Xilinx Answer 12786): 4.1i iMPACT - "ERROR:iMPACT:131 - (Spartan-IIE device) not supported in Slave Serial mode."

{SP1} (Xilinx Answer 12543): 4.1i iMPACT - A third-party BSDL file causes iMPACT to close without error messages.
{SP1} (Xilinx Answer 12541): 4.1i iMPACT - 9500/XL/XV - iMPACT erases devices that have been read-protected.

MAP
{SP3 } (Xilinx Answer 12574): 4.1i Virtex-II MAP - A crash occurs when I use the "-timing" option.
{SP3 } (Xilinx Answer 13177): 4.1i Virtex-II MAP - Packer creates shapes that are inconsistent with carry logic placement, leading to unroutes and "WARNING:Place:1855".
{SP3 } (Xilinx Answer 12718): 4.1i Virtex-II MAP - "FATAL_ERROR:Pack:pksv2slice.c:333:1.16.18.1 - Unable to create route through signal..."
{SP3 } (Xilinx Answer 12610): 4.1i Virtex-II MAP - "FATAL_ERROR:Map:Port_Main.h:116:1.17 - This application has discovered an exceptional condition from which it cannot recover."
{SP3 } (Xilinx Answer 13346): 4.1i Virtex-II MAP - DPRAM RPM that worked in 3.1i is not placeable in 4.1i

{SP2 } (Xilinx Answer 12564): 4.1i Virtex-E MAP - "FATAL_ERROR: MapLib:basmmfrag.c:1180:1.24 - Number of out pins not equal to 1."
{SP2 } (Xilinx Answer 12704): 4.1i Virtex-II MAP - The mapper is rejecting a valid Virtex-II clock-forwarding scheme.
{SP2 } (Xilinx Answer 12463): 4.1i Virtex-II MAP - "FATAL_ERROR:Pack:pktv2rpmutil.c:150.1.1.2.1 - Exceeded the max number of shapes in an RMP."
{SP2 } (Xilinx Answer 12703): 4.1i Virtex-II MAP - MAP is dropping AREA_GROUP constraints for RAM16x1Ds.
{SP2 } (Xilinx Answer 12888): 4.1i Virtex-II MAP - Multiple RAM16X1D components are not getting packed into slices as 16x2 DPRAMs.

{SP1} (Xilinx Answer 11756): 4.1i Virtex-II - Are there restrictions on IBUFG, DCM, and BUFG routing in Virtex-II devices?
{SP1} (Xilinx Answer 11836): 4.1i Virtex-II MAP - Crash occurs when PAD drives both BUFGMUX and DCM.
{SP1} (Xilinx Answer 11917): 4.1i Virtex-II MAP - IOB (programmable) delay is incorrectly turned "On" for an IOB with a DCM-based clock.
{SP1} (Xilinx Answer 12306): 4.1i Virtex-E MAP - Area group constraints are handled differently between 3.1i and 4.1i.
{SP1} (Xilinx Answer 12423): 4.1i Virtex MAP - An incorrect MAP error occurs because of a GCLKIOB miscount.
{SP1} (Xilinx Answer 12434): 4.1i Virtex-II PAR - Problems routing Interleaver Core design in XC2V8000.
{SP1} (Xilinx Answer 12534): 4.1i MAP - "ERROR:DesignRules:486 - Blockcheck: Invalid DCM feedback loop."
{SP1} (Xilinx Answer 12551): 4.1i MAP - "ERROR:Pack:311" is reported when I am using RPM_GRID.

Modular Design
{SP2 } (Xilinx Answer 12654): 4.1i Virtex-II PAR - Modular Design Assembly fails with: "INTERNAL_ERROR:Place: basplprcntl.c:2539:1.38 - Cannot place component."

{SP1} (Xilinx Answer 12528): 4.1i Modular Design, PAR - "FATAL_ERROR: Route:basrtsanity.c:169:1.8 - Process will terminate."

NGD2EDIF
{SP3 } (Xilinx Answer 12979): 4.1i EDIF2NGD - Netlist connectivity is lost/ "ERROR:MapLib:32 - LUT2 symbol "xx" has an equation that uses an input pin connected to a trimmed signal..."

{SP2 } (Xilinx Answer 12489): 4.1i NGD2EDIF - INITSTATE property is missing from the GTS net of the EDIF file in the Foundation flow.

NGD2VER
none

NGD2VHDL
{SP2 } (Xilinx Answer 12838): 4.1i NGD2VHDL - When NGD2VHDL is used with the -r switch, incorrect logic is produced. (VHDL)

NGDANNO
{SP3 } (Xilinx Answer 13020): 4.1i NGDAnno - Timing values for a Virtex-II multiplier model differ between the timing report and SDF files.
{SP3 } (Xilinx Answer 13373): 4.1i NGDAnno - "FATAL_ERROR: Anno:ResolverImp.c:549:1.11 - Semantic check failed for physical block..."

{SP2 } (Xilinx Answer 12840): 4.1i NGDAnno - "FATAL_ERROR:Anno:basnadelay.c:448:1.17 - Block "rx_son_d_N(10)" (P200) has invalid clock pin 23 .. "

NGDBUILD
{SP2 } (Xilinx Answer 12878): 4.1i NGDBUILD Virtex-II design crashes the machine. (This occurs only on PCs with AMD processors.)

PACKAGE FILES
none

PAR
{SP3 } (Xilinx Answer 13270): 4.1i Virtex-II PAR - PC memory usage in Virtex-II designs.
{SP3 } (Xilinx Answer 13344): 4.1i Virtex-II PAR - PAR crashes during the load of a guide design.
{SP3 } (Xilinx Answer 13343): 4.1i Virtex-II PAR - TBUFs are placed in conflict with locked TBUFs.
{SP3 } (Xilinx Answer 13342): 4.1i Virtex-II PAR - The placer crashes during the Clustering phase.
{SP3 } (Xilinx Answer 13340): 4.1i Virtex-II PAR - The placer is not taking clock analysis into account for Block RAMs.
{SP3 } (Xilinx Answer 13270): 4.1i Virtex-II PAR - PC memory usage in Virtex-II designs.
{SP3 } (Xilinx Answer 12561): 4.1i Virtex-II PAR - A crash occurs when Constructive Placer is run.

{SP2 } (Xilinx Answer 11384): 4.1i Virtex-II PAR - Placer rejects valid BUFGMUX configurations.
{SP2 } (Xilinx Answer 12385): 4.1i Virtex-II PAR - Guided PAR crashes on a PC, or "INTERNAL_ERROR:SpeedCalc: basndmain.c:240:1.29 - getloaddelay called..." is reported.
{SP2 } (Xilinx Answer 12758): 4.1i PAR - Router incorrectly exits if timing score is zero, but there are still unrouted nets.
{SP2 } (Xilinx Answer 12694): 4.1i Virtex-II PAR - Placer crashes when the carry chain is longer than the device height.
{SP2 } (Xilinx Answer 12605): 4.1i Virtex-II PAR - "FATAL_ERROR:Route:basrtsanity.c:169:1.8 - Process will terminate."
{SP2 } (Xilinx Answer 12604): 4.1i Virtex-II PAR - Placer prints confusing messages about "Overlapping range constraints".
{SP2 } (Xilinx Answer 12619): 4.1i Virtex-II PAR - Placer does not report Directed Placer failures.
{SP2 } (Xilinx Answer 12702): 4.1i Virtex-II PAR - DDR IOBs may be placed in an unroutable configuration.
{SP2 } (Xilinx Answer 12883): 4.1i Virtex-II PAR - PAR hangs after the line "Generating PAR Statistics".
{SP2 } (Xilinx Answer 12603): 4.1i Virtex-II PAR - Placer fails with no error messages.
{SP2 } (Xilinx Answer 12889): 4.1i Virtex-E PAR Router exited routing in first router iteration without meeting timing.
{SP2 } (Xilinx Answer 12890): 4.1i Virtex-II PAR - Placer crashes after clock logic placement if I/Os are partially LOC'd.

{SP1} (Xilinx Answer 12433): 4.1i Virtex-E PAR - Router may overload buffers, leading to underreporting of timing.

PROJECT NAVIGATOR
{SP3 } (Xilinx Answer 12934): 4.1i HDL Bencher - Selecting "Generate Expected Simulation Result" causes "Exit code 0005".
{SP3 } (Xilinx Answer 13304): 4.1i ISE - When converting to 4.1i, Project Navigator ABEL-XST projects from 3.3i are not converted to ABEL-XST-VHDL.
{SP3 } (Xilinx Answer 12584): 4.1i Project Navigator - The MAP property "map to input function" does not include 7 or 8 as an option for Virtex-II.
{SP3 } (Xilinx Answer 12570): 4.1i Foundation ISE Project Navigator - Enabling local feedback results in error that includes "cpldfit.tcl - Done: failed with exit code: 65535."
{SP3 } (Xilinx Answer 13302): 4.1i ISE - Neither Timing Analyzer, FPGA Editor, nor PROM File Formatter tools appear on top of Project Navigator when launched on Windows 2000.
{SP3 } (Xilinx Answer 12078): 4.1i Project Navigator - Project snapshots created in ISE 3.x cannot initially be viewed in the ISE 4.x Snapshots tab.
{SP3 } (Xilinx Answer 11798): 4.1i ISE - Project Navigator attempts to checkout a Synplify Pro license when synthesizing with Synplfy.

{SP2 } (Xilinx Answer 12251): 4.1i Project Navigator - Unable to select post-route EDIF/VHDL/Verilog (timing) simulation netlist
{SP2 } (Xilinx Answer 12787): 4.1i ISE - Timing Report cannot be viewed from a snapshot.
{SP2 } (Xilinx Answer 12509): 4.1i ISE - Errors appear when CoolRunner-II packages are implemented with Auto-FG and Auto-CS Packages selected.
{SP2 } (Xilinx Answer 12788): 4.1i ISE - When "Delete Implementation Data" is run, the <module name>.udo file is deleted.
{SP2 } (Xilinx Answer 12789): 4.i1 ISE - A "jc2_ver" tutorial example contains invalid Verilog syntax.

{SP1} (Xilinx Answer 12229): 4.1i Project Navigator - "Delete Implementation Data" fails with Exit Code 65535 on designs with schematic sources.
{SP1} (Xilinx Answer 12530): 4.1i ISE - Project Navigator on Solaris: Help:Find function does not work.
{SP1} (Xilinx Answer 12531): 4.1i ISE - "Delete Implementation Data" is not removing the EDN file in Spectrum Flow with remote sources.
{SP1} (Xilinx Answer 12532): 4.1i ISE - Setting a custom .do file using "browse" results in a ModelSim error.
{SP1} (Xilinx Answer 12239): 4.1i XST - XST reports an error on the second run of a synthesis. (The first run synthesized successfully).
{SP1} (Xilinx Answer 12253): 4.1i Project Navigator - Project Navigator XST properties are ignored by XST.
{SP1} (Xilinx Answer 12254): 4.1i Virtex-E PAR - 4.1i Project Navigator - Error in script_cpldfit.tcl: "Invalid command name "-nomlopt".

PROM FILE FORMATTER
{SP1} (Xilinx Answer 12522): 4.1i PROMGen - No XC17S300A support is available in the 4.1i software.

SIMPRIMS
{SP1} (Xilinx Answer 12553): 4.1i UniSim, SimPrim - Warning: "CHAN_BOND_MODE is not in OFF,MASTER,SLAVE_1_HOP,SLAVE_2_HOPS"

SPEED FILES
{SP1} (Xilinx Answer 12201): 4.1i Install - What are the latest speed files for the Spartan-II and Virtex families?

TIMING
{SP2 } (Xilinx Answer 12385): 4.1i Virtex-II PAR - Guided PAR crashes on a PC, or "INTERNAL_ERROR:SpeedCalc: basndmain.c:240:1.29 - getloaddelay called..." is reported.
{SP2 } (Xilinx Answer 12169): 4.1i Trace (TRCE)/Timing Analyzer - The source and destination in the path header may not match those in the detail path.
{SP2 } (Xilinx Answer 12021): 4.1i Trace (TRCE) - Path reports the net to the destination component, but no setup time or propagation delay.

UNISIM
{SP2 } (Xilinx Answer 12795): 4.1i SIMPRIMS - The CLKFX signal in the DCM SimPrim VHDL model does not work in Post-NGDBuild simulation. (VHDL)
{SP2 } (Xilinx Answer 12467): 4.1i SimPrims - Incorrect results are reported when a back-annotated simulation is performed with Block Memory primitives.

{SP1} (Xilinx Answer 12553): 4.1i UniSim, SimPrim - Warning "CHAN_BOND_MODE is not in OFF,MASTER,SLAVE_1_HOP,SLAVE_2_HOPS"
{SP1} (Xilinx Answer 12552): 4.1i UniSim - When I simulate a Block RAM with UniSim, PORT A does not function correctly.

XST
{SP3 } (Xilinx Answer 13292): 4.1i XST - XST generates incorrect logic because of a function that converts a string-to-std_logic_vector.
{SP3 } (Xilinx Answer 12712): 4.1i XST - "FATAL_ERROR:Xst:fctutil.c:1022:1.20".
{SP3 } (Xilinx Answer 13286): 4.1i XST - XST generates incorrect logic when a loop variable, signal, and/or port all have the same name.
{SP3 } (Xilinx Answer 13285): 4.1i XST - "ERROR:Xst:829 - file_name.vhd (Line xx). Constant Value expected for Generic 'generic_name'."
{SP3 } (Xilinx Answer 13284): 4.1i XST - "ERROR: NgdBuild:604 - logical block 'block_name' with type 'lut433' is unexpanded. Symbol 'lut433' is not supported in target 'virtex'."
{SP3 } (Xilinx Answer 13283): 4.1i XST - "ERROR: Xst:826 - file_name.vhd (Line xx). Statement mod is not supported yet."
{SP3 } (Xilinx Answer 13282): 4.1i XST - "ERROR: Xst:826 - file_name.vhd (Line xx). Statement WhileLoop is not supported yet."

{SP2 } (Xilinx Answer 12744): 4.1i XST - XST is ignoring the FAST slew property.
{SP2 } (Xilinx Answer 12749): 4.1i XST - An XST design hangs on an AMD Athlon-based computer.
{SP2 } (Xilinx Answer 12891): 4.1i XST - XST is not passing RLOC properties.
{SP2 } (Xilinx Answer 12892): 4.1i XST - "ERROR:MapLib:111 - MULT_AND symbol "instance_name" (output signal=instance_name) has multiple fanouts."
{SP2 } (Xilinx Answer 12893): 4.1i XST - XST is implementing IOBUFDS incorrectly.
{SP2 } (Xilinx Answer 12895): 4.1i XST - XST handles VHDL libraries improperly.
{SP2 } (Xilinx Answer 12896): 4.1i XST - XST Virtex-II timing reports do not contain the correct timing values.
{SP2 } (Xilinx Answer 12897): 4.1i XST - XST hangs during low-level optimization.
AR# 13223
Date Created 11/19/2001
Last Updated 04/28/2006
Status Archive
Type General Article