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# AR# 13241

## Description

General Description:

A dynamically variable shift register LUT (SRL) is an SRL that can vary the shift amount based on the address inputs of the SRL. (For more information on SRLs, please refer to the Libraries Guide at http://support.xilinx.com/support/library.htm.)

How do I infer a dynamically variable shift register LUT for the Virtex architecture?

## Solution

The following example is taken from the Synplify Pro User Guide (C:\Synplicity\synplify_70\doc), pages 4-80:

VHDL example:

library IEEE;

use IEEE.std_logic_1164.all;

entity srltest is

port ( inData: std_logic_vector(7 downto 0);

clk, en : in std_logic;

outStage : in integer range 3 downto 0;

outData: out std_logic_vector(7 downto 0));

end srltest;

architecture rtl of srltest is

type dataAryType is array(3 downto 0) of std_logic_vector(7 downto 0);

signal regBank : dataAryType;

begin

outData <= regBank(outStage);

process(clk, inData) begin

if (clk'event and clk = '1') then

if (en='1') then

regBank <= (regBank(2 downto 0) & inData);

end if;

end if;

end process;

end rtl;

The following example is taken from the Synplify Pro User Guide (C:\Synplicity\synplify_70\doc), pages 4-80:

Verilog example:

module test_srl(clk, enable, dataIn, result, addr);

input clk, enable;

input [3:0] dataIn;

input [3:0] addr;

output [3:0] result;

reg [3:0] regBank[15:0];

integer i;

always @(posedge clk) begin

if (enable == 1) begin

for (i=15; i>0; i=i-1) begin

regBank[i] <= regBank[i-1];

end

regBank[0] <= dataIn;

end

end

assign result = regBank[addr];

endmodule

AR# 13241
Date 05/14/2014
Status Archive
Type General Article
Page Bookmarked