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AR# 13292

4.1i XST - XST generates incorrect logic because of a function that converts a string-to-std_logic_vector


Keywords: VHDL, function, string, std_logic_vector

Urgency: Standard

General Description:
If I perform a string conversion-to-std_logic_vector function in VHDL, incorrect logic is generated.


This problem is fixed in the latest 4.1i Service Pack, available at:
The first service pack containing the fix is 4.1i Service Pack 3.
AR# 13292
Date Created 11/30/2001
Last Updated 08/06/2003
Status Archive
Type General Article