We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13301

HDL Bencher - Does this tool write out VHDL and Verilog files along with the testbench waveform?


Keywords: HDL Bencher, Verilog, test fixture, VHDL, testbench, export, write

Urgency: Standard

General Description:
I see the testbench waveform that HDL Bencher created in my "Sources in Project" window; does HDL Bencher write out VHDL and/or Verilog code as well?


Yes, VHDL and Verilog files are being created along with the waveforms in the project directory.

The extensions for the files are:

VHDL testbench:

Verilog test fixture:

Starting in 11.1, Xilinx will no longer support the Test Bench Waveform Editor. When a project with a test bench waveform (TBW) is upgraded to 11.1, the TBW will be automatically converted to an HDL test bench and added to the project. Xilinx recommends using HDL test benches for new projects. For more information about creating an HDL test bench, go to:

- ISE Language Templates for starter examples
- Application Note XAPP199, Writing Efficient Test Benches
- Synthesis and Simulation Design Guide in software manuals.
AR# 13301
Date Created 08/29/2007
Last Updated 10/16/2008
Status Archive
Type General Article