We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13311

Signal and Power Integrity - Does Xilinx offer any SI design resources?


Keywords: signal, power, integrity, SI, PCB, crosstalk, couple, coupling, reflection, ring, terminate, termination, EMI, bypass, decouple, decoupling, caps, capacitors, via, land, IBIS, SPICE, simulation, simulate, HyperLynx, SPECCTRAQuest, SSO, SSN, simultaneous, switching, output, noise, voltage, amplitude, ground, bounce, supply, distribution, system, ripple, GHz, Gbps, gigabit, I/O, IO, serial, CDR, SERDES, transmission, line, AC, attenuation, BER, bit, error, rate, test, channel, bond, chip, chirp, CML, LVDS, LVPECL, differential, signal, common, mode, comma, running, disparity, DC, balance, jitter, deterministic, random, dispersion, equalization, pre-emphasis, pre, emphasis, conditioning, eye, diagram, mask, rise, fall, rising, falling, time, timing, margin, budget, characteristic, impedance, match, trace, microstrip, offset, stripline, edge, RF, UI, unit, interval, skin, effect, loss, depth, tangent, thermal

What resources does Xilinx offer regarding Signal Integrity Engineering?


Xilinx has identified and published best practices for Signal Integrity (SI) engineering. The Signal Integrity resources are available under the Technology Solutions category on the Xilinx home page:
Navigation path: Home Page: Technology Solutions -> Signal Integrity.

URL for the landing page is:

Other resources pertaining to power supply bypassing, gigabit signaling, IBIS/SPICE simulation, and other areas of SI Engineering are constantly being added and updated in the various device User Guides available in the Documentation Center.

Of significant value are:

1. WP323: Signal Integrity: Tips and Tricks

2. XAPP863: Using Digitally Controlled Impedance: Signal Integrity vs. Power Dissipation Considerations

3. XAPP707 - Advanced ChipSync Applications

The following documents cover several design guidelines on Signal Integrity:

1. FPGA User Guide (All Virtex family User Guides)
2. Spartan-3 Generation User Guide
3. PCB Designers Guide (for Virtex-4, Virtex-5, and Virtex-6)
4. RocketIO Multi-Gigabit Transceiver User Guide (Virtex-4, Virtex-5, and Virtex-6)
5. RocketIO Transceiver Signal Integrity Simulation Kits

Xilinx Education Services also provides a training course on Signal Integrity for High-Speed Memory and Processor I/O. Course Description and registration information are available at:
AR# 13311
Date Created 08/29/2007
Last Updated 09/29/2009
Status Active
Type General Article