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AR# 13312

Virtex-II/Pro/-4 Data Sheet - What is the maximum Tin (input signal transition time)?

Description

What is the maximum Tin (input signal transition time) for Virtex-II or Virtex-II Pro devices?

This number is presented in the Virtex-E data sheet: DC and Switching Characteristics -> DC Characteristics -> "Recommended Operation Conditions":

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Virtex-E&iLanguageID=1

However, it is not available in the newer Virtex data sheets (see below).

Solution

The Tin is not specified for Virtex-II, Virtex-II Pro and Virtex-4 devices, as it represents an endorsement of poor design techniques.

Virtex-II devices have a Schmidt trigger or a comparator for all inputs. For inputs with a comparator (VREF), the logic level is determined by the comparator. For LVTTL/LVCMOS, the logic level is determined by the minimum hysterysis.

Generally, slow input transitions should be avoided for the following reasons:

1. Poor design timing -- you do not know precisely when the threshold is crossed.

2. More power consumption -- the input consumes extra mA while in the threshold.

3. More susceptibility to noise -- the input picks up noise from the board and from ground bounce while near the threshold.

Hence, Tin is design-dependent.

In a slow design, combinatorial signals are allowed to be slow. Clocks should always be fast, as any ringing or ground bounce can lead to double-triggering.

AR# 13312
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article