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AR# 1337

SYNPLIFY: How to apply the DRIVE property using the xc_props attribute?

Description

Keywords: Verilog, VHDL, Synplify, DRIVE, LVTTL

Urgency: Standard

General Description:
How to apply the DRIVE property using the xc_props attribute?

The DRIVE property is applied to IOB output components OFD,
OBUF, OBUFT, IOBUF instances (with implied LVTTL standards).

For the XC4000XV, XC4000XLA, and SpartanXL, DRIVE programs
the output drive current from High (24 mA) to Low (12 mA).

For Virtex and Spartan2, DRIVE selects output drive strength (mA)
for the components that use the LVTTL interface standard.

Solution

1

// Verilog

module ff_example (CLK, D_IN, Q_OUT);
input CLK;
input [3:0] D_IN;
output [3:0] Q_OUT /* synthesis xc_props="DRIVE=24" */;

reg [3:0] Q_OUT;

// D flip-flop
always @(posedge CLK)
Q_OUT <= D_IN;

endmodule

2

-- VHDL

library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;

entity fast_ex is
port (CLK : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (3 downto 0);
Q_OUT : out STD_LOGIC_VECTOR (3 downto 0));
attribute xc_props of Q_OUT : signal is "DRIVE=24";
end fast_ex;

architecture XILINX of fast_ex is

begin

-- D flip-flop
process(CLK)
begin
if rising_edge(CLK) then
Q_OUT <= D_IN;
end if;
end process;

end XILINX;
AR# 1337
Date Created 10/09/1996
Last Updated 04/23/2007
Status Archive
Type General Article