We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13455

4.1i TSim CoolRunner - A negative edge-triggered flip-flop fails timing simulation


Keywords: 4.1i, 4.2i, CPLD, XPLA3, CoolRunner, timing, Neg Edge

Urgency: Standard

General Description:
Negative edge-triggered flip-flops do not work properly in timing simulation for XPLA3 -- they behave as if they are positive edge-triggered FFs.


This problem is fixed for global clocks in the 4.2i software.

For product term clocks, this problem is fixed in 4.2i Service Pack 2, available at:
The first service pack containing the fix is 4.2i Service Pack 2.

Examining the timing simulation file reveals that there is a double inversion on the clock signals. You may work around this by manually removing one level of inversion. This will not affect timing, as the inversion delay is already taken into consideration in the product term propagation delay.
AR# 13455
Date Created 01/03/2002
Last Updated 08/05/2003
Status Archive
Type General Article