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AR# 13458

3.6.x FPGA Express - The STARTUP component is being removed (Spartan and 4K families) from my design without warning

Description

Keywords: Spartan, 4K, Verilog, VHDL, STARTUP

Urgency: Standard

General Description:
FPGA Express removes the STARTUP primitive from the design before optimization. (This can occur in both VHDL and Verilog designs.)

Solution

1

VHDL:

If this occurs in a VHDL design, place a "dont_touch" attribute on the instantiation in the HDL code to prevent the STARTUP primitive from being removed. This must be done within the code (as opposed to with the FPGA Express Constraints Editor), as the component is removed before the attribute can be applied within the editor.

For example:
...
component STARTUP port
(GSR, GTS, CLK : in STD_LOGIC;
Q1Q4, Q2, Q3 : out STD_LOGIC );
end component;

attribute fpga_dont_touch : string;
attribute fpga_dont_touch of U1 : label is "true";

begin

U1 : STARTUP port map
(GSR => reset,
GTS => tri_state,
CLK => clock,
Q1Q4 => sig1,
Q2 => sig2,
Q3 => sig3);
...

For this particular design, it is not necessary to use all of the ports on the STARTUP block; rather, list only the ports that will be used.

2

Verilog:

If this occurs in a Verilog design, create an empty module declaration for the component that is being removed. This will define the port directions and allow FPGA Express to insert the component correctly.

For Example:
...
STARTUP U1 (.GSR(reset), .GTS(tri_state), .CLK(clock), .Q1Q4(sig1), .Q2(sig2), .Q3(sig3));
...
endmodule

module STARTUP (GSR, GTS, CLK, Q1Q4, Q2, Q3, DONEIN);
input GSR, GTS, CLK;
output Q1Q4, Q2, Q3, DONEIN;
endmodule

For this particular design, it is not necessary to use all of the ports on the STARTUP block; rather, list only the ports that will be used.
AR# 13458
Date Created 01/03/2002
Last Updated 08/11/2003
Status Archive
Type General Article