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AR# 13469

Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - After configuration, device draws high current and becomes hot

Description

Urgency: Hot

General Description:

After I configure the first Virtex device in a serial daisy-chain consisting of more than one Virtex device, the first Virtex device draws a great deal of current and becomes hot.

Solution

Virtex/-E, Spartan-II/-IIE

When a Virtex/-E or Spartan-II/-IIE device is configured with an incorrect bitstream, the device draws a high amount of current and becomes very hot. During configuration, all Virtex devices search for the same synchronization word (0xAA995566). If a bitstream for one Virtex device is sent to another Virtex device, the second device always attempts to configure. For example, if an XCV400 bitstream is sent to a V50, the V50 attempts to configure, and can draw high current and become hot.

When multiple Virtex/-E or Spartan-II/-IIE devices are arranged in a serial daisy-chain to be configured from one or more 18V00 PROM devices, this problem can occur if the 18V00 PROM tries to send configuration information before its I/Os are active. While unusual, this can occur as described in the following scenarios:

NOTE: Virtex-II devices do not exhibit this problem because Virtex-II bitstreams are embedded with device-specific information.

Scenario 1: Board power-up is non-monotonic or the 18V00 is not completely powered down before being powered up

18V00 devices are sensitive to board power-up issues, and must be completely powered down before being powered up. If board power-up is non-monotonic, or if the board is not completely powered down before being powered up, the 18V00's internal address counter might be incremented before the device's I/Os are functional.

To avoid this problem:

- Ensure that the 18V00 device is powered down to 0 volts before power-up, and ensure that power-up is monotonic.

- Avoid clocking the PROM. Hold off the CCLK (for instance by holding INIT low from power-up during the programming phase) until the PROM is fully powered.

- Immediately clear the FPGA of a bad bitstream. Toggle the PROGRAM pin of the target FPGA immediately after the completion of the XC18V00 programming operation by issuing the "Load FPGA" instruction through the JTAG chain if the PROM CF pin is tied to the Virtex PROG pin (as recommended in the 18V00 data sheet).

Scenario 2: Embedded SVF solutions

In embedded SVF-based programming solutions, a certain RUNTEST instruction might be too brief, which can cause the 18V00's internal address counter to increment before its I/Os become active. Consequently, the synchronization word for the first Virtex device is never issued, and the synchronization word for the second Virtex is recognized by the first.

To correct this problem, manually increase the RUNTEST parameter (wait time) following all NORMRST instruction loads in the SVF. See the table below for recommended RUNTEST parameter values.

Device..........RUNTEST parameter*...................Equivalent Wait Time

XC18V04......1600000 TCK cycles @ 1 MHz....1600 msec

XC18V02......800000.........................................800 msec

XC18V01......400000.........................................400 msec

XC18V512....200000.........................................200 msec

XC18V256....110000.........................................110 msec

* The RUNTEST parameters specified in this table assume for default Master-Serial Virtex/-E a CCLK rate of 4 MHz (worst case = 2.8 MHz)

Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3

The high current draw for the Virtex and Spartan family can also occur under certain programming sequences. This problem can occur when iMPACT programs a PROM that is connected to the FPGA. If the PROM and FPGA are initially empty on power-up, then it is possible that an incomplete bitstream is delivered from the PROM to the FPGA during the iMPACT programming procedure. Specifically, the PROM can deliver an incomplete bitstream to the FPGA during the programming of the PROM. Occasionally, the result of the high-current draw on the FPGA can cause a power supply to drop and cause the iMPACT verify operation on the PROM to fail.

One way to avoid this issue is to hold the INIT pin of the FPGA low on power-up. Release the INIT pin after the PROM is configured so that the FPGA can be loaded correctly.

AR# 13469
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article