UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13489

2.1 System Generator for DSP - When a multi-channel FIR is used, simulation mismatch errors are reported during VHDL simulation

Description

Keywords: Finite Impulse Response, DSP, SysGen, generate, functional

Urgency: Standard

General Description:
In Simulink, I have used the FIR block and have generated a multi-channel FIR in my design. When I run VHDL simulation, simulation mismatch errors are reported.

Solution

This problem is in the VHDL wrapper that is written out by the System Generator. This is NOT a bug in the FIR filter (EDIF netlist) that is created from CORE Generator. If anything other than a Gateway-In or a multi-rate block (such as an up or down sampler) is connected to the inputs of the multi-channel FIR block, these errors will occur.

Please contact the Xilinx hotline for more information (1-800-255-7778).
AR# 13489
Date Created 01/07/2002
Last Updated 06/22/2004
Status Archive
Type General Article