When I use a StateCAD-generated VHDL source file and testbench in ModelSim for functional simulation, no problems are reported. However, when I attempt timing simulation, several errors occur, including:
"Error: Incompatible mode for port"
"Fatal Error: SDF file requires Xilinx primitive library"
The problem is that StateCAD sometimes uses ports of mode BUFFER, while the Xilinx back-end tools do not use this mode when generating the post-route VHDL model. This causes a mismatch when the design is loaded into ModelSim.
An alternative is to implement testbenches using Xilinx Waveform Editor. The testbenches then work at all levels, because the port maps are updated automatically using the original design and the exported netlists.