When I load a design with a VCD file, the following warning messages appear:
"WARNING:Power:163 - PowerVcd_Dump: Declaration of variable 'testbench.a.v1.sl.gsuh_v1_acc_s_smp_clk.i' ignored, identifier code'"' is already in use by 'testbench.a.v1.sl.v1_acc_s_smp'!:
"WARNING:Power:164 - PowerVcd_Dump: Subsequent redeclarations of this or other identifier codes will be ignored without comment."
The warnings are usually seen when the "-r" option is used while the VCD file is generated from within ModelSim.
Do not use the "-r" switch with ModelSim's VCD add command or specify a number of levels other than 1 to the $dumpvars Verilog task. In addition to these warnings, an unnecessarily large VCD file will be created if the "-r" option is used.
If the "-r" option is not being used (or 1 has been specified to the $dumpvars Verilog task), the warnings are still occasionally seen. The warnings can be ignored under these circumstances. ModelSim is re-specifying the same identifier for a dependant net (i.e., XPower automatically calculates the activity rate [or frequency] of this net and does not need this information from the VCD file).