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AR# 13567

4.1i Timing Analyzer/TRCE - Timing does not report the skew between differential pair n-side and p-side routing for LVPECL or LVDS signals

Description


General Description:

Timing Analysis does not report the skew between differential pair n-side and p-side signals. How do I know when the signal is valid?

Solution


The 4.2i software tools report this for LVPECL; LVDS signal reporting will be included in a future software version.



Meanwhile, you can view the delay through each side by querying the delay time in FPGA Editor.
AR# 13567
Date Created 08/29/2007
Last Updated 03/08/2011
Status Archive
Type General Article