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AR# 13572

Virtex-E/Virtex-II/Pro - Simultaneous Switching Output (SSO) guidelines for LVDS and LVPECL

Description

General Description:

The Simultaneous Switching Output (SSO) guidelines for Virtex-E and Virtex-II omit entries for LVDS and LVPECL. What is the recommended maximum number of SSOs for these signals?

Solution

(For a detailed discussion about handling SSOs, please see (Xilinx XAPP689): "Managing Ground Bounce in Large FPGAs.")

For SSO guidelines, use these substitutions:

Virtex-E, LVDS: one output pair = one LVTTL 2mA driver with fast slew rate

Virtex-E, LVPECL: one output pair = one LVTTL 24mA driver with fast slew rate

The Virtex-II/Pro LVPECL driver is identical to the Virtex-E driver.

Because the Virtex-II LVDS driver is very balanced, its switching causes a negligible amount of transient current. As a result, SSOs are not a problem. For more information, please see (Xilinx Answer 12629).

The Virtex-E SSO guidelines are provided in the Virtex-E data sheet at:

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Virtex-E&iLanguageID=1

Select "Detailed Functional Description" -> "Using SelectI/O" -> "Design Considerations" -> "Simultaneous Switching Guidelines".

The Virtex-II SSO guidelines are provided in the "Virtex-II Platform FPGA User Guide" at:

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/User+Guides/FPGA+Device+Families/Virtex-II/&iLanguageID=1

Select "Design Considerations" -> "Using Single-Ended Select I/O Ultra Resources" -> "Design Considerations" -> "SSO Guidelines".

AR# 13572
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article