What are some items to check when my timing simulation results in incorrect logic?
1. If registers do not appear to be toggling, see (Xilinx Answer 15564).
2. Re-implement the design with the fastest speed-grade device (perhaps a logic path is not running quickly enough).
3. Re-implement the design with the optimization strategy set to "Speed" rather than to "Balance" or "Density." This will instruct the fitter to flatten logic, resulting in faster overall logic paths.
4. Re-implement with macrocells set to high-speed (instead of low-power) mode.
NOTE: This applies only to the XC9500/XL/XV families.
5. Slow the clock frequency. This helps to determine if setup time violations exist.
6. Add or tighten timing constraints on failing paths.