When I generate a timing constraint, in the TWR/TWX timing report, the setup/hold time of input register does not match the data sheet number.
The TRCE report (TWX or TWR file) shows that the IOB register setup/hold window is 200 ps (using Virtex-II 1.94 speed files for -5 in an XC2V6000), as follows:
This does not match the TIOPICK/TIOICKP (pad, no delay) stated in Table 14, page 9 of the data sheet:
The data sheet number for Virtex-II -5 is:
TIOPICK: 0.96 ns
TIOICKP: - 0.39 ns
In addition, the TPSDCM does not match. TRCE reported the following in TWX/TWR file:
Based on the report:
TPSDCM = 1.175 (data path) - ( - 0.505) (clock path) = 1.67 ns.
No TPHDCM report.
On page 25 of the Data Book, Table 31 (http://support.xilinx.com/partinfo/ds031-3.pdf) reports the TPSDCM/TPHDCM for 2V6000-5 as: 1.70/-0.9 ns.
This is a resolved known issue -- TRCE and Timing Analyzer were not reporting these numbers correctly. The data sheet numbers for setup/hold times are correct.
This problem is fixed in the latest 4.2i Service Pack, available at:
The first service pack containing the fix is 4.2i Service Pack 3.