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AR# 13671

4.1i CORE Generator, Virtex-II, Asynchronous FIFO - Under what circumstances will the WR_ERR and the RD_ERR signals be activated?

Description

Keywords: Asynchronous FIFO, WR_ERR, RD_ERR

Urgency: Standard.

General Description:
For Asynchronous FIFO, under what circumstances will the WR_ERR and the RD_ERR signals be activated?

Solution

The only time RD_ERR is active (goes high) is when the FIFO stack is empty and an attempt to read from the stack has been made.

The only time WR_ERR is active (goes high) is when the FIFO stack is full and an attempt to write to the stack has been made.
AR# 13671
Date Created 01/22/2002
Last Updated 10/09/2003
Status Archive
Type General Article