When I perform a static timing analysis, the following warning occurs:
"WARNING:Timing:2491 - No timing constraints found, doing default enumeration."
What does this warning mean? Is it serious? How do I avoid it?
Static timing analysis is performed by analyzing a design against the user-specified timing constraints. Without constraints, the static timing tools would have little to report. If the timing tools are not given any constraints, the system automatically creates common constraints through a process called default enumeration, and it analyzes the design against these constraints. (This is similar to advanced analysis (-a) in TRACE, or Analyze -> Analyze Against Auto-Generated Constraints in Timing Analyzer.)
This process can be useful for obtaining a quick estimate of a design's performance. However, you should constrain your designs for higher Quality of Results (QoR) during the place-and-route process.
For information on how to constrain a design, use the Xilinx Constraints Editor.