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AR# 13756

Virtex-II/-II Pro FPGA, DCM - What causes phase error, duty cycle distortion, and excessive jitter on DCM clock outputs (VCCAUX, droop, dip, ripple, CLK2X period)?

Description

When I use the Virtex-II or Virtex-II Pro DCM, excessive jitter, a distorted duty cycle, and distorted period clock outputs result from the internal ground pins that are disturbed by I/O or CLB switching. This occurs even while the LOCKED signal is High.

What might cause this?

Solution

The internal ground pin is shared by the DCMs, the IOBs, and the CLBs. When there is a large change in VCCINT current or VCCO current (or both), there is a corresponding change in the IR (voltage) drop and a resulting drop change in the DCM power supply.

The internal drop of the DCM power supply will result in phase errors, duty cycle distortion, and excessive jitter on DCM clock outputs.

To prevent this, design the power supply so that the change in voltage over time is slow enough that the DCM can update its taps quickly enough to operate without creating excessive jitter or period distortion.

The following practices might help to reduce jitter or period distortion:

1. Use the "Simultaneously Switching Outputs (SSO)" guidelines and proper bypassing/decoupling for best performance. For more information on SSO, see (Xilinx Answer 11713) />
For power bypassing/decoupling guidelines, refer to (Xilinx XAPP623): "Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors":

http://www.xilinx.com/support/documentation/application_notes/xapp623.pdf

and the PCB Checklist at:

http://www.xilinx.com/products/design_resources/signal_integrity/si_pcbcheck.htm


2. Increase the FACTORY_JF setting to "FFFF." The DCM updates its taps approximately every 20 input clocks when the "FACTORY_JF" attribute is set to 0xFFFF. (The default settings of 0xC080h result in updates that occur more slowly.) Note that a well-decoupled and stable power supply is the preferred solution.

Increasing the FACTORY_JF setting might introduce a small amount of jitter (~30 ps) because the DCM frequently updates its delay line (this is why FACTORY_JF is not set to the maximum value by default). If the power supply is unstable, the phase error introduced might be much bigger than the extra jitter introduced; consequently, increasing the FACTORY_JF setting might improve the design.

3. Limit changes in power supply or ground potentials to less than 10 mV in any 1 ms interval; this allows the DCM to properly track out the change (see figure below).

4. Limit the noise at the power supply to within 200 mV peak-to-peak (see figure below).



VCC droop
VCC droop


5. If VCCAUX and VCCO are of the same power plane, every VCCAUX/VCCO pin must be properly decoupled/bypassed. If your design uses DCM, Xilinx recommends that you separate VCCAUX from VCCO if guidelines 3 and 4 above cannot be maintained.

6. If the voltage change cannot be prevented, place strong I/O drivers physically away from the DCM or use additional IOBs as extra ground pins (virtual grounds) on either side of the DCM; this will reduce the internal IR drop and improve the jitter. You can create a "virtual ground" by configuring an IOB as an output driving GND ("0" logic level) and additionally grounding the I/O pins externally directly to the ground plane.

7. The CLK2X output is especially affected by the power or ground shift. Consequently, using the CLKFX output with M=2 and D=1 might provide a better quality output when all IOBs and CLBs are switching. The CLKFX circuitry updates the tap every three input clocks in the DFS mode (as opposed to the slower update rate for the CLK2X output).

The Factory_JF attribute can be modified using the FPGA Editor, a VHDL/Verilog attribute, or the UCF file.

FPGA Editor

1. Open the NCD file in a "read/write" edit mode.

2. Open the DCM block and change the FACTORY_JF attribute to the appropriate setting.

3. Save the NCD file.

VHDL

attribute FACTORY_JF : string;
attribute FACTORY_JF of <dcm_inst> : label is "FFFF";

Verilog

//synthesis attribute FACTORY_JF of <dcm_inst> is "FFFF"

UCF

INST <dcm_inst> FACTORY_JF = "FFFF";

NOTE: Setting the jitter filter so that it updates more frequently does not change the magnitude of the jitter by a significant amount. Rather, it changes the rate at which the jitter is occurring by shifting the spectral density up in frequency.
AR# 13756
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-II
  • Virtex-II Pro
  • Virtex-II Pro X
  • Virtex-II QPro/R
IP
  • Digital Clock Manager (DCM) Module