UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1376

Foundation XVHDL: Using Global Set/Reset and STARTUP

Description


Keywords: GSR, Startup, Metamor

Versions: F6.x, F1.3/F1.4

Urgency: Standard

General Description:

Xilinx FPGAs have a dedicated Global Reset net which, when
asserted, will asynchronously initialize all flip-flops in
the device (set or reset for the XC4000 families; reset only
for the XC3000 and XC5200 families).

**Note that this solution applies to the Metamor XVHDL compiler
only. If using the Express HDL compiler, Express will
automatically infer the STARTUP block for 4K/5K families if
there is a common reset signal connected to all of the
registers in the design.

Solution

1

XC3000 Family
-------------
The XC3000 family devices have a dedicated RESET pin (active
low), which is connected to the Global Reset network.
Nothing special needs to be added to your VHDL code in order
to use this RESET capability.

If your design already contains a signal which asynchronously
resets all flip-flops, and you want to replace its function
with the dedicated RESET pin, the 'Xilinx_GSR' attribute may
be used to strip out your reset signal from the Xilinx
netlist. The flip-flops in the resulting design can only be
reset by driving the RESET pin on the device low.

Refer to the section titled "Examples" for an example of
using the 'Xilinx_GSR' attribute.

2

Examples
--------

--********************************************************
--Example of instantiating STARTUP. This example is for an --XC4000 design. For an XC5200 design, replace GSR with GR.

library IEEE;
use IEEE.std_logic_1164.all;

entity USE_GSR is
port (RESET, IN1, CLK: in std_logic;
OUT1: out std_logic);

end USE_GSR;

architecture TEST of USE_GSR is

component STARTUP
port (GSR: in std_logic);
end component;

begin

--Instantiate STARTUP, and map RESET to the Global Reset net
U1: STARTUP port map (GSR => RESET);

process (CLK, RESET)
begin
if RESET='1' then
OUT1 <= '0';
elsif (CLK'event and CLK='1') then
OUT1 <= IN1;
end if;
end process;

end TEST;

--*******************************************************
-- Example using an active-low signal to drive the GSR pin
-- of the STARTUP symbol.

library IEEE;
use IEEE.std_logic_1164.all;

entity INV_GSR is
port (RESET, IN1, CLK: in std_logic;
OUT1: out std_logic);
end INV_GSR;

architecture ACTIVE_LOW of INV_GSR is

signal RESETN: std_logic;

component STARTUP
port (GSR: in std_logic);
end component;

begin

RESETN <= not RESET;

U1: STARTUP port map (GSR => RESETN);

process (CLK, RESETN)
begin
if RESETN = '1' then
OUT1 <= '0';
elsif (CLK'event and CLK = '1') then
OUT1 <= IN1;
end if;
end process;

end ACTIVE_LOW;

--*****************************************************
--Example of using XILINX_GSR attribute to remove RESET
--signal from netlist. Use this for 3K designs, or for
--4K or 5K designs where the STARTUP symbol is on a
--top-level schematic.

library IEEE;
use IEEE.std_logic_1164.all;

entity USE_GSR is
port (RESET, IN1, CLK: in std_logic;
OUT1: out std_logic);

--Declare the Xilinx_GSR attribute and use it to remove the
--RESET signal from the synthesized Xilinx netlist
attribute Xilinx_GSR: boolean;
attribute Xilinx_GSR of RESET: signal is true;

end USE_GSR;

architecture TEST of USE_GSR is

begin

process (CLK, RESET)
begin
if RESET='1' then
OUT1 <= '0';
elsif (CLK'event and CLK='1') then
OUT1 <= IN1;
end if;
end process;

end TEST;

3

XC4000 and XC5200 Families
--------------------------
The XC4000 and XC5200 family devices allow any signal, either
external or internal, to serve as the global reset signal.

To use this dedicated Global Reset with Foundation VHDL, the
STARTUP symbol must be instantiated in the design, with your
set/reset signal connected to the GSR (XC4000) or GR (XC5200)
pin of the STARTUP symbol.

It is not necessary to include your set/reset signal in the
behavioral descriptions of the flip-flops in the design. Any
signal that is used to behaviorally set/reset a flip-flop
will not use the dedicated Global Reset network, and that
set/reset signal will be OR'ed with the Global Reset signal
to asynchronously set/reset that flip-flop.


Note: The STARTUP symbol is not functionally simulatable.

Refer to the section titled "Examples" for an example of
using the STARTUP symbol and the 'Xilinx_GSR' attribute.
AR# 1376
Date Created 10/16/1996
Last Updated 01/02/2000
Status Archive
Type General Article