We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13791

Virtex-II Configuration - The INIT pin goes Low during configuration


What does it mean when the INIT pin goes Low during configuration?


If the INIT pin goes Low, a frame error has occurred, which indicates that the configuration data being sent to the FPGA is incorrect. Common causes of this include the following:

- Corrupted data (especially in custom configuration solutions such as microprocessors)

- Signal integrity problems on the data/CCLK signals

- Powering problems

During configuration, CRC checks are embedded in the bitstream. If CRC fails, the INIT pin is pulled Low indicating a frame error and the device stops configuring. Generally, this means that the device is getting an incorrect bit or bits, or the bitstream is not correct. If the INIT pin goes Low, it does mean that the device is synchronized and is recognizing packets.

If the device is configured in serial mode, see (Xilinx Answer 8110). You can embed LOUT writes to see where the error occurs, and the DIN data should be correlated back to the bit file to check for agreement.

If incorrect data occurs at other times throughout the bitstream, the INIT pin goes Low because explicit CRC checks are failing. However, if signal integrity errors occur during a packet header or other commands, INIT may not always go Low. See (Xilinx Answer 8240) for more information.

To indicate more precisely where the problems occur for serial modes, the "debug bitstream" process described in (Xilinx Answer 4219) is helpful.

AR# 13791
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article