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AR# 13792

6.1i CPLDFit - ERROR:CPLD:832 - net is assigned to an invalid location (Px) for this device or This pin does not support the functionality of that signal

Description

General Description:

When I run implementation in Project Navigator, a message similar to one of the following occurs:

"ERROR:CPLD:832 - 'net' is assigned to an invalid location ('PX') for this device. This will prevent the design from fitting on the current device. 'net' must be reassigned before attempting a re-fit."

"ERROR:Cpld:6 - Cannot assign Output Pin moda to PX* (FB1_4). This pin does not support the functionality of that signal."

*PX - X is a pin number.

Solution

To solve this problem, check the following:

- Check the device data sheet to see if "PX" is a dedicated pin that cannot be used for I/O (e.g., JTAG pin, VCC, GND, etc.)

- Ensure that you are using the proper notation for location constraints:

a) Example for pinned packages (PC, VQ, TQ, HQ), where "y" is the pin number:

NET DATAIN LOC = Py;

b) Example for ball-grid packages (FG, BG, CS), where "x" is the row letter and "y" is the column number:

NET DATAIN LOC = xy;

- Be sure that you have not placed a PROHIBIT constraint on that same location.

Data sheets are available at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

CoolRunner XPLA3 Only

If you are attempting to utilize the JTAG pins as I/O, ensure that you have de-selected "Reserve ISP Pins" in the software.

AR# 13792
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article