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AR# 13893

4.2i XST - Support for concatenation of slices in an array

Description

Keywords: concat, slice, array, VHDL, 4.2i

Urgency: Hot

General Description:
XST now supports concatenation of vectors into an array in VHDL. What is this type of syntax?

Solution

The syntax specifically for concatenation of vectors into an array is as follows:

:
:
type My_Array is array (1 downto 0) of std_logic_vector (2 downto 0);
:
signal IDATA : std_logic_vector (2 downto 0);
signal QDATA : std_logic_vector (2 downto 0);
signal IDATA : std_logic_vector (2 downto 0);

signal I_DATA_REG : My_Array;
signal Q_DATA_REG : My_Array;
:
:
I_DATA_REG <= (IDATA, QDATA);
Q_DATA_REG <= I_DATA_REG(0 downto 0) & PDATA;
:
AR# 13893
Date Created 02/19/2002
Last Updated 08/06/2003
Status Archive
Type General Article