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AR# 13920

12.1 Known Issue - Timing Analyzer - My FROM:TO constraint picks up the wrong paths (TNM)

Description


How do the TNM and TNM_NET grouping constraints work? I would like to ignore a path between "flopa" and "flopb," passing through net "netand" using a TIG constraint setup like the one shown below. (I would like to remove the information between the double-dashed lines below from timing analysis with the TIG.)
TNM Circuit
TNM Circuit


I am specifying my FROM and TO flip-flops using the TNM_NET grouping constraint.

My UCF:

#PERIOD Constraint
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 7 ns HIGH 50 %;

#Create Groups
NET "neta" TNM_NET = "neta_grp";
NET "netand" TPTHRU = "netand_thru";
NET "netb" TNM_NET = "netb_grp";

#Actual Constraint
TIMESPEC "TS_broken_TIG" = FROM "neta_grp" THRU "netand_thru" TO "netb_grp" TIG;





But it does not seem to work. What is wrong?

================================================================
Timing constraint: PATH "FROM neta_grp THRU netand_thru TO netb_grp" TIG ;

0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------

Nothing has been analyzed, and the path is still in the PERIOD constraint:

=================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 7 nS HIGH 50.000000 % ;

2 items analyzed, 0 timing errors detected.
Minimum period is 1.744ns.
--------------------------------------------------------------------------------
Slack: 5.389ns (requirement - (data path - negative clock skew))
Source: flopa
Destination: flopb
Requirement: 7.000ns
Data Path Delay: 1.611ns (Levels of Logic = 3)
Negative Clock Skew: 0.000ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 7.000ns

Data Path: flopa to flopb
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
---------------------------------------------------------------------------
SLICE_X4Y0.YQ Tcko 0.449 neta
flopa
SLICE_X0Y0.G4 net (fanout=1) 0.521 neta
SLICE_X0Y0.Y Tilo 0.347 netb
SLICE_X0Y0.DY net (fanout=1) 0.001 netand
SLICE_X0Y0.CLK Tdyck 0.293 netb
flopb
------------------------------------------------------------------------------
Total 1.611ns (1.089ns logic, 0.522ns route)
(67.6% logic, 32.4% route)




--------------------------------------------------------------------------------

Is this a bug?

Solution


No. If you place both TNM and TNM_NET on a net, they both trace forward and pick up all the flip-flops that are encountered downstream; they do not move backward. In this case, "neta_grp" contained "flopb," and "netb_grp" contained "flopc." The FROM and TO constraints tried to remove the green dashed line, but because the THRU point "netand" did not exist, the FROM:THRU:TO constraint came up empty.

How to fix this

From Timing Analyzer, choose Analyze --> Query TimeGroups:

#-------------------------------------------------------------------------------
# TimeGroups Report
# Design: H:\PROJECTS\timing\tnmtest.ncd
# Physical Constraints File: H:\PROJECTS\timing\tnmtest.pcf
# Generated: Tue Jan 22 18:07:58 2002
# Release 4.1.03i - Timing Analyzer E.30
#-------------------------------------------------------------------------------

TimeGroup neta_grp:
BELs:
flopb

TimeGroup netand_thru:
Pins:
xlxi_6.D

TimeGroup netb_grp:
BELs:
flopc



Simply specify the nets that come before the flip-flops, not after. Instead, use nets "din" and "neta" to create the groups:

#PERIOD Constraint
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 7 ns HIGH 50 %;

#Create Groups
NET "din" TNM_NET = "neta_grp";
NET "netand" TPTHRU = "netand_thru";
NET "neta" TNM_NET = "netb_grp";

#Actual Constraint
TIMESPEC "TS_broken_TIG" = FROM "neta_grp" THRU "netand_thru" TO "netb_grp" TIG;

In this case, it works:
================================================================
Timing constraint: PATH "FROM neta_grp THRU netand_thru TO netb_grp" TIG ;

1 item analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------
Delay: 1.611ns (data path - negative clock skew)
Source: flopa
Destination: flopb
Data Path Delay: 1.611ns (Levels of Logic = 3)
Negative Clock Skew: 0.000ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 7.000ns

Data Path: flopa to flopb
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------------------------
SLICE_X4Y0.YQ Tcko 0.449 neta
flopa
SLICE_X0Y0.G4 net (fanout=1) 0.521 neta
SLICE_X0Y0.Y Tilo 0.347 netb
SLICE_X0Y0.DY net (fanout=1) 0.001 netand
SLICE_X0Y0.CLK Tdyck 0.293 netb
flopb
----------------------------------------------------------------------------
Total 1.611ns (1.089ns logic, 0.522ns route)
(67.6% logic, 32.4% route)
--------------------------------------------------------------------------------

In addition, the path has disappeared from the PERIOD constraint.

Q: Why should I use "neta" instead of "netand"? Will not the TNM_NET pick up only the AND gate?

A: No. TNM and TNM_NET generally pick up only FLOPs, RAMs, and PADs. The AND gate is invisible to them.

What is the difference between TNM and TNM_NET?

TNM will trace backwards if you place it on the net before the IBUF, grabbing the IPAD. Otherwise, you would have no way to group input pads, as no nets are driving them.
AR# 13920
Date Created 08/29/2007
Last Updated 05/13/2012
Status Active
Type Known Issues
Tools
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  • ISE Design Suite - 11.1
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