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AR# 13936

Virtex-II Pro RocketIO - Fibre Channel Compliance


Are Virtex-II Pro RocketIO transceivers fully Fibre Channel Compliant?


RocketIO transceivers are electrically compliant with Fibre Channel specifications for 1 and 2 Gbps operation. Electrical compliance information for Fibre Channel is located in the RocketIO Characterization Report. The Characterization Report is available in the SPICE lounge and can be accessed by registering here:

1. Select the tab for the family you are interested in.

2. Look under Data Files and select Spice Models.

3. Select the Device Models tab found to the left of screen.

4. Under HSPICE and Eldo Models, click on the link to the family you want.

5. Click on link to the SPICE Model link.

6. Sign in to Xilinx. If you are new, click on the Create Account button.

7. After reading the license agreement, click the "I Accept" button.

8. The File Download dialog box will appear. Open or Save the zip file.

If the CRC of the RocketIO transceiver block is not used, the end-of-packet ordered set is not automatically changed to maintain the disparity required for 1G and 2G Fibre Channel (see the RocketIO User Guide, Chapter 3, CRC section for details). In this case, the user must manually send the correct end-of-packet character to maintain the disparity required by Fibre Channel. This requires the user to maintain the running disparity in the fabric and present the correct EOP character to the RocketIO transceiver. See (Xilinx Answer 14607) for a code example that accomplishes this.

RocketIO transceivers have too much latency on the TX and RX paths for the Arbitrated Loop topology of 1G and 2G Fibre Channel.

The specification requires a maximum delay of six word times from receiving data to passing it back to the TX side when the transceiver is simply closing the loop (not sending or receiving). RocketIO transceivers cannot meet this requirement.

The latency requirement is a problem only with a large ring. The specification allows for up to 128 nodes with six cycles of latency. This means that a signal has 768 clks (plus some cable propagation time) to get around the loop before the sender times out and invalidates any receive data thereafter. Consequently, you can have 128 nodes with six cycles of delay, 64 nodes with 12 cycles of delay, 32 nodes with 24 cycles of delay, and so on and still have a working design.

There is also an issue with clock correction with Arbitrated Loop. Clock correction sequences contain the "lane_id" of each node on the loop, which means that there are up to 128 different sequences on a loop. Since RocketIO cannot support this many sequences, clock correction must be done in the fabric.

AR# 13936
Date 12/15/2012
Status Active
Type General Article