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AR# 14000

4.1i NGD2EDIF - References to OSC4 cause a Netlist Fatal error in Timing Simulation

Description

Keywords: OSC4, NGD2EDIF, Foundation, Logic, Simulator, Error 9432, Netlist Fatal error

Urgency: Standard

General Description:
During back annotation, NGD2EDIF should suppress the writing out of oscillator instance/nets. This was not occurring with 4.1i Service Pack 3; thus the back-annotated EDIF netlist contains references to OSC4. This causes the following errors when Timing Simulation is run with Foundation Logic Simulator:

"EDIF netlist 'c:\xilinx\active\projects\test4i\xproj\ver1\rev1\time_sim.edn' loading v.2.99.1.10
C:\xilinx\active\projects\test4i\xproj\ver1\rev1\time_sim.edn(130): missing cell 'OSC4'
Error 9432: Netlist fatal error was detected."

The OSC4 instance/nets should be suppressed because there is not a simulation model for the OSC4. Instead, the user forces the clock signal with the Foundation Logic Simulator.

Solution

1

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 1.

2

If you do not yet have 4.2i Service Pack 1, a resolution is to remove all references to OSC4 in the back-annotated EDIF netlist.
AR# 14000
Date Created 08/29/2007
Last Updated 08/15/2003
Status Archive
Type ??????