We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14014

Virtex-II Pro Developer's Kit - Running "make fpga" leads to the error: "No rule to make target `par/v2/top_ip.edf'..."


Keywords: V2PDK, make

Urgency: Standard

General Description:
When I run the step "make fpga" in the reference platforms, the following error message occurs:

"*** No rule to make target `par/v2/top_ip.edf', needed by `par/v2/top_ip.ngd'. Stop."


Before running Step 4 ("make fpga"), you must run Step 3 ("make synth"). This generates the target for "make fpga"
AR# 14014
Date Created 08/29/2007
Last Updated 10/01/2008
Status Archive
Type General Article