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AR# 14028

XST - "ERROR:HDLParsers:715 - file_name.vhd Line xx. Attribute on units are only allowed on current unit"

Description

When I run the synthesis process, the following error is reported:

"ERROR:HDLParsers:715 - file_name.vhd Line xx. Attribute on units are only allowed on current unit."

Solution

This problem can occur when the attribute on line "xx" is not declared in the VHDL code.

In VHDL, constraints can be described with attributes. Before a constraint can be used, it must be declared with the following syntax:

attribute attribute_name : <type>;

For example:

attribute RLOC : string;

An attribute can be declared in an entity or architecture. If declared in the entity, the attribute is visible in both the entity and the architecture. If the attribute is declared in the architecture, it cannot be used in the entity declaration. Once it has been declared, you can specify a VHDL attribute as follows:

attribute attribute_name of {component_name | label_name | entity_name | signal_name | variable_name}: {component | label | entity | signal | variable} is attribute_value;

Accepted attribute_values for depend on the attribute type.

Examples:

entity my_top is

port (D : in std_logic;

:

:

attribute LOC : string;

attribute LOC of D : signal is "P24";

end entity;

attribute INIT : string;

attribute RLOC : string;

attribute bufg : string;

attribute INIT of FD : component is "1";

attribute RLOC of u123 : label is "R11C1.S0";

attribute bufg of my_clock: signal is "clk";

For Xilinx products, the most common objects are "signal", "component", and "label". (A label describes an instance of a component.) Please remember that VHDL is case-insensitive.

More information about entering attributes please refer XST user guide.

AR# 14028
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article