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AR# 14047

XST - "ERROR:Xst:827 - file_name Line xx: Signal xx cannot be synthesized, bad synchronous description."

Description

When I attempt to infer synchronous elements (registers, flip-flops, memories, etc.), the following error message is reported:

"ERROR:Xst:827 - file_name (Line xx). Signal xx cannot be synthesized, bad synchronous description."

A typical scenario for the above error message would be VHDL code similar to the following:

:

:

process (c, r) is begin

if r'event and r = '1' then

q <= '0';

elsif c'event and c = '1' then

q <= d;

end if;

end process;

:

:

or

:

:

process (c, r) is begin

if (r = '1' ) then

q <= '0';

if c'event and c = '1' then

q <= d;

end if;

end if;

end process;

:

:

Solution

Although your VHDL code might be syntactically correct, XST supports predefined templates for inferring various types of synchronous elements.

The synchronous element description is based on the 'event VHDL attribute. In order for XST to infer a synchronous element, the 'event VHDL attribute must be present in the topmost "IF" statement of your process. Furthermore, there should be no embedded 'event statements within a process. The following two examples illustrate this point:

Example 1:

:

:

synchronous_description : process (clk, reset) is begin

if clk'event and clk = '1' then -- topmost if statement

if reset = '1' then -- synchronous reset

q <= '0';

else

q <= d;

end if;

end if;

end process;

:

:

In the above example, there are no embedded 'event statements. In addition, the 'event statement is part of the topmost "IF" statement. Beneath the topmost "IF" statement is a description that will infer a synchronous reset. More embedded "IF" statements can be added to your design as necessary.

Example 2:

:

:

synchronous_description : process (clk, reset) is begin

if reset = '1' then -- asynchronous reset

q <= '0'; -- you can have embedded if statements if you need to

elsif clk'event and clk = '1' then -- still the topmost if statement

q <= d; -- you can put your case statements here or

end if; -- embed more if statements but not

end process; -- any more 'event statements

:

:

In the above example, there are no embedded 'event statements. In addition, the 'event statement is part of the topmost "IF" statement because it is associated with the "ELSIF" statement. More VHDL code can be inserted underneath the topmost "IF" statement as your design requires.

Inference templates can also be found in the ISE Templates and XST user guide in the software manuals. http://www.xilinx.com/support/software_manuals.htm

AR# 14047
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article