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AR# 1408

CPLD 9500/XL/XV CoolRunner-II/XPLA3 - What should be done with the unused JTAG pins of a Xilinx CPLD?

Description

Can the unused JTAG pins of a Xilinx CPLD device be left unconnected?

The devices addressed by this Answer Record are:

  • XC9500 (XC95--- )
  • XC9500XL(XC95---XL)
  • XC9500XV (XC95---XV)
  • XPLA3 (XCR3---XL)
  • CoolRunner-II (XC2C---)

Solution

XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 have internal pull-ups on TDI and TMS.

CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK.

Xilinx recommends using external pull-up resistors on the JTAG input pins, TDI, TMS, and TCK. The value of these resistors can be customized per your application and JTAG chain length; for a single device the value of 4.7k Ohm is suggested.

Internal pull-up resistors are present on these JTAG input pins. However, external termination will allow for increased tolerance of noisy environments.

For XPLA3 devices, tie the Port-Enable pin to ground if the JTAG pins are dedicated for JTAG use. For more information on Port-Enable, see (Xilinx Answer 8455).

For other common CPLD questions, see the CPLD FAQ (Xilinx Answer 24167).

AR# 1408
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • 9500
  • 9500XL
  • 9500XL IQ
  • More
  • 9500XL XA
  • 9500XV
  • CoolRunner XPLA3
  • CoolRunner-II
  • CoolRunner-II XA
  • Less