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AR# 14080

4.1i XST - "ERROR:Xst:930 - <file>.v Line xx. Lval '<signal>' cannot be a net"

Description

Keywords: XST, Verilog, 930, Lval, net, assign

Urgency: Standard

General Description:
When a Verilog source file is compiled, XST issues the following error:

"ERROR:Xst:930 - <file>.v Line xx. Lval '<signal>' cannot be a net."

Solution

This error occurs when a signal has been declared as a net data type instead of a register data type.

When you assign values within procedural assignment statements, use a register data type (typically "reg") to store information from one assignment to the next.
AR# 14080
Date Created 03/06/2002
Last Updated 08/06/2003
Status Archive
Type General Article