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AR# 14081

XST - "ERROR:HDLCompilers:42 - .v Line xx. Illegal left hand side of procedural continuous assignment."


General Description:

When a Verilog source file is compiled, XST issues the following error:

"ERROR:HDLCompilers:42 - <file>.v Line xx. Illegal LHS of procedural continuous assignment."


This error occurs when a signal has been declared as a register data type instead of a net data type.

When you perform a continuous assignment in a concurrent statement, use a net data type (typically "wire") to allow data to be instantly updated.

AR# 14081
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article