When I run timing simulation on a design that contains multiple driver tristate networks, the net delay is pessimistic for some paths. Generally, net delays are modeled in the SDF file as input port delays on the component that is driven by the net. When multiple tristate components have the same destination, there are multiple net delays, but only one of the delays can be modeled; the software picks the worst case delay. For instance, consider the following example:
TBUF1 -> LOAD1 : net delay = 400 ps
TBUF2 -> LOAD1 : net delay = 600 ps
TBUF3 -> LOAD1 : net delay = 500 ps
The net delay of 600 ps is put onto the input port of LOAD1. In timing simulation, it appears that the net delay from all three TBUFs to LOAD1 is 600 ps.
As a result, a timing simulation can report setup violations, even if the design meets timing.
To work around this issue, use LUT mapping for these paths rather than TBUFs. You can use the MAP "-tx" switch to automatically re-map TBUFs into LUTs.