UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14109

4.1i XST - "ERROR:Xst:1044 - <file>.v Line xx. Part-select is outside limits set by declaration of '<my_bus>'"

Description

Keywords: XST, Verilog, bus, limits, select, 1044

Urgency: Standard

General Description:
During the compilation of my Verilog source, XST reports the following error:

"ERROR:Xst:1044 - <file>.v Line xx. Part-select is outside limits set by declaration of '<my_bus>'"

Solution

When accessing signals within Verilog, XST requires that the data type (register or net) be declared before it is used. If a bussed "inout" port is accessed before it is declared as a "reg" or a "wire", the above error will result.

To avoid this error, place the type declaration statement in your code before the bus is used.

Sample code:

inout [7:0] mybus;
...
wire [7:0] mybus;
...
assign blah = mybus;
assign mybus = foo[7:0];
AR# 14109
Date Created 03/07/2002
Last Updated 08/06/2003
Status Archive
Type General Article