UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14175

5.1i NGDBuild - Is it possible to constrain a bus with "NET "signal_name" LOC=P32, P33, P34;" from the pin-locking section of the UCF template?

Description

Keywords: bus, NET, UCF, NGDBuild, LOC, constraints, 4.1i, 5.1i

Urgency: Standard

General Description:
Is it possible to constrain a bus with "NET "signal_name" LOC=P32, P33, P34;" from the pin-locking section of the UCF template?

Solution

No -- this constraint may only be used to constrain a single signal to a range of pins. For example, in the following constraint, "signal_name" will be assigned to either P32, P33, or P34:

NET "signal_name" LOC=P32, P33, P34;

The only way to assign bus signals to pins is to break the bus down, and assign it to the pins. For example, in the following constraint, "bus_name<2:0>" will be assigned to P32, P33, and P34 respectively:

NET "bus_name<2>" LOC=P32;
NET "bus_name<1>" LOC=P33;
NET "bus_name<0>" LOC=P34;
AR# 14175
Date Created 03/13/2002
Last Updated 03/06/2005
Status Archive
Type General Article